The present invention relates to the field of programmable devices, and the systems and methods for programming the same. Programmable devices, such as FPGAs, typically includes thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops, and memory. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
A typical design cycle for determining the configuration of a programmable device, referred to as compilation, starts with an extraction phase, followed by a logic synthesis phase, a fitting phase, and an assembly phase. The extraction phase takes a user design, typically expressed as a netlist in a hardware description language such as Verilog or VHDL, and produces a set of logic gates implementing the user design. In the logic synthesis phase, the set of logic gates is permuted over the hardware architecture of the programmable device in order to match elements of the user design with corresponding portions of the programmable device. The fitting phase assigns the various portions of the user design to specific logic cells and functional blocks (sometimes referred to as placement) and determines the configuration of the configurable switching circuit used to route signals between these logic cells and functional blocks (sometimes referred to as routing), taking care to satisfy the user timing constraints as much as possible. In the assembly phase, a configuration file defining the programmable device configuration is created. The configuration can then be loaded into a programmable device to implement the user design. Programmable devices can be configured with the configuration file during or after manufacturing.
The compilation of a user design from a netlist to a configuration file is performed by one or more circuit compilation software applications. Quartus IL a product of the Altera Corporation, is an example of a prior art circuit compilation software application used to program programmable devices such as field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and structured ASICs.
To satisfy the design goals of a user design, the compilation software can apply one or more additional optimization algorithms to optimize the user design. Optimization algorithms can optimize a user design with respect to one or more of a number of different design goals, including overall execution speed, programmable device resource consumption, and power consumption.
Typically, compilation software includes a large number of different optimization algorithms that can be potentially applied to a user design. Input parameter settings select one or more of these optimization algorithms to be applied to a user design and specify the configurations of these selected optimization algorithms. Example input parameter settings may activate or modify the performance of optimization algorithms such as physical synthesis and register packing. Typically, compilation software includes default input parameter settings that are tailored to meet reasonable design goals for a representative sample of user designs. However, for any given user design, there may be alternative input parameter settings that provide better optimizations with respect to one or more design goals.
When users desire to maximize a design's performance with respect to one or more design goals, they may experiment with different input parameter settings. The Design Space Explorer is a prior software application provided by the Altera Corporation that assists users in determining input parameter settings tailored to a specific user design that provide better optimizations than the default input parameter settings. The Design Space Explorer compiles the user design multiple times with different randomly selected input parameter settings. For each compilation of the user design, the Design Space Explorer evaluates the performance of the user design configuration with respect to one or more design goals to determine which input parameter settings provide the best performance.
The Design Space Explorer is capable of evaluating all possible combinations of input parameter settings. As a result, the Design Space Explorer can find an optimal set of input parameter settings for any user design. However, this exhaustive search of all possible combinations of input parameter settings is often extremely time consuming and requires large amounts of computing resources. This discourages users from using the Design Space Explorer, especially when under a deadline. Additionally, the search time for the Design Space Explorer increases rapidly (often exponentially) as the number of input parameter settings increase. To decrease the search time of the Design Space Explorer, developers of circuit compilation software sometimes limit the number of input parameter settings by hard-coding the configuration settings of some optimization algorithms, rather than allowing users to specify the configuration of these optimization algorithms. Although this decreases the search time of the Design Space Explorer, it results in the hard-coded optimization phases performing sub-optimally for many user designs.
It is therefore desirable for a system and method to identify input parameter settings for user designs that provide better results than default input parameter settings without an exhaustive search of all possible combinations of input parameter settings.